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Title: Scalable linear array architectures for matrix inversion using Bi-z CORDIC
Authors: Luo, J. W.
Jong, Ching Chuen
Keywords: DRNTU::Engineering::Electrical and electronic engineering
Issue Date: 2011
Series/Report no.: Microelectronics journal
Abstract: In this paper, VLSI array architectures for matrix inversion are studied. A new binary-coded z-path (Bi-z) CORDIC is developed and implemented to compute the operations required in the matrix inversion using the Givens rotation (GR) based QR decomposition. The Bi-z CORDIC allows both the GR vectoring and rotation mode, as well as division and multiplication to be executed in a single unified processing element (PE). Hence, a 2D (2 dimensional) array consisting of PEs with different functionalities can be folded into a 1D array to reduce hardware complexity. The Bi-z CORDIC also eliminates the arithmetic complexity of the angle quantization and formation computation that exist in the traditional CORDIC. Two mapping techniques, namely a linear mapping method and an interlaced mapping method, for mapping a 2D matrix inversion array into a 1D array are proposed and developed. Consequently two corresponding array architectures are designed and implemented. Both the architectures use the Bi-z CORDIC in their PEs and they are designed to be fully scalable and parameterizable in terms of matrix size and data wordlength. The linear mapping method is a straightforward mapping offering simple schedule and control signals. The interlaced mapping method has a more complicated schedule with complex control signals but achieves 100% or near 100% processor utilization for odd and even size matrix, respectively.
DOI: 10.1016/j.mejo.2011.10.009
Rights: © 2011 Elsevier Ltd.
Fulltext Permission: none
Fulltext Availability: No Fulltext
Appears in Collections:EEE Journal Articles

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