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Title: A look up table design with 3D bipolar RRAMs
Authors: Chen, Yi-Chung
Zhang, Wei
Li, Hai
Keywords: DRNTU::Engineering::Computer science and engineering
Issue Date: 2012
Source: Chen, Y.-C., Zhang, W., & Li, H. (2012). . 17th Asia and South Pacific Design Automation Conference.
Abstract: Look Up Table (LUT) is a basic configurable logic element in Field Programmable Gate Arrays (FPGAs). In a commercial product, Static Random Access Memory (SRAM) has been widely used in each LUT to store configured logic. Recently, emerging Resistive RAM (RRAM) has attracted a lot of attention for its high density and non-volatility. In this work, we explore a novel LUT design with bipolar RRAM devices. To obtain design efficiency, a 3D high-density interleaved memory structure is introduced in the proposed LUT. The corresponding peripheral circuits were developed with TSMC 0.18μm technology node. Compared to the traditional SRAM-based FPGA, the RRAM-based LUT demonstrates advantages such as a eliminating initialization stage, a much higher density with 56% area reduction, a bit-addressable write scheme, dynamic reconfiguration, and better flexibility in supporting various configurations.
DOI: 10.1109/ASPDAC.2012.6165051
Fulltext Permission: none
Fulltext Availability: No Fulltext
Appears in Collections:SCSE Conference Papers

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