Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/99004
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dc.contributor.authorChen, Yi-Chungen
dc.contributor.authorZhang, Weien
dc.contributor.authorLi, Haien
dc.date.accessioned2013-07-31T02:41:55Zen
dc.date.accessioned2019-12-06T20:02:13Z-
dc.date.available2013-07-31T02:41:55Zen
dc.date.available2019-12-06T20:02:13Z-
dc.date.copyright2012en
dc.date.issued2012en
dc.identifier.citationChen, Y.-C., Zhang, W., & Li, H. (2012). . 17th Asia and South Pacific Design Automation Conference.en
dc.identifier.urihttps://hdl.handle.net/10356/99004-
dc.identifier.urihttp://hdl.handle.net/10220/12538en
dc.description.abstractLook Up Table (LUT) is a basic configurable logic element in Field Programmable Gate Arrays (FPGAs). In a commercial product, Static Random Access Memory (SRAM) has been widely used in each LUT to store configured logic. Recently, emerging Resistive RAM (RRAM) has attracted a lot of attention for its high density and non-volatility. In this work, we explore a novel LUT design with bipolar RRAM devices. To obtain design efficiency, a 3D high-density interleaved memory structure is introduced in the proposed LUT. The corresponding peripheral circuits were developed with TSMC 0.18μm technology node. Compared to the traditional SRAM-based FPGA, the RRAM-based LUT demonstrates advantages such as a eliminating initialization stage, a much higher density with 56% area reduction, a bit-addressable write scheme, dynamic reconfiguration, and better flexibility in supporting various configurations.en
dc.language.isoenen
dc.subjectDRNTU::Engineering::Computer science and engineeringen
dc.titleA look up table design with 3D bipolar RRAMsen
dc.typeConference Paperen
dc.contributor.schoolSchool of Computer Engineeringen
dc.contributor.conferenceAsia and South Pacific Design Automation Conference (17th : 2012 : Sydney, NSW)en
dc.identifier.doihttp://dx.doi.org/10.1109/ASPDAC.2012.6165051en
item.grantfulltextnone-
item.fulltextNo Fulltext-
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