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|Title:||uBRAM-based run-time reconfigurable FPGA and corresponding reconfiguration methodology||Authors:||Chen, Yi-Chung
|Keywords:||DRNTU::Engineering::Computer science and engineering||Issue Date:||2012||Source:||Chen, Y.-C., Wang, W., Zhang, W., & Li, H. (2012). uBRAM-based run-time reconfigurable FPGA and corresponding reconfiguration methodology. 2012 International Conference on Field-Programmable Technology (FPT), 80-86.||Abstract:||With rising demands for high-performance computing and design flexibility of post-fabrication system, reconfigurable architecture has been drawing increasing attentions. However, reconfigurability, advantage of current Field-Programmable Gate Array (FPGA), is severely limited by small capacity of on-chip Static Random Access Memory (SRAM) for storing configuration bits. With emerging high-density and high-performance nano memory devices, opportunities are provided to improve the reconfigurability of the current FPGA's design. In this paper, we demonstrate a novel design of run-time reconfigurable FPGA architecture with distributed unified Block Random Access Memory (uBRAM) based on dense and fastaccess non-volatile memory. The uBRAMs are distributed into the architecture and functioned as unified memory blocks. It can be freely switched between data memory for temporary data storage or configuration memory for configuration bits storage. Such a design supports run-time reconfiguration; meanwhile, it avoids the dedicated area overhead of configuration memory suffered in previous designs. As a consequence, significant area saving and superior design flexibility can be achieved. To fully explore the potential of the proposed architecture, corresponding methods of run-time reconfiguration with uBRAM are introduced, including external/internal run-time reconfiguration, and self-adapting reconfiguration. We take Resistive Random Access Memory (RRAM) as an example of qualified nano memory for case study. The RRAM cells in the uBRAM are aggregated in a 3D High-density Interleaved Memory (3D-HIM) structure to further save area cost. Compared to the conventional FPGA which supports only partial runtime reconfiguration with specific design, experimental results demonstrate the judicious benefits of the proposed architecture on the area saving and the superior design flexibility without scarifying performance requirements and power consumption.||URI:||https://hdl.handle.net/10356/99393
|DOI:||10.1109/FPT.2012.6412116||Fulltext Permission:||none||Fulltext Availability:||No Fulltext|
|Appears in Collections:||SCSE Conference Papers|
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