Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/99786
Full metadata record
DC FieldValueLanguage
dc.contributor.authorHosseini, S. M. Ehsanen
dc.contributor.authorGoh, Wang Lingen
dc.contributor.authorChan, Kheong Sannen
dc.date.accessioned2010-08-31T03:04:11Zen
dc.date.accessioned2019-12-06T20:11:27Z-
dc.date.available2010-08-31T03:04:11Zen
dc.date.available2019-12-06T20:11:27Z-
dc.date.copyright2009en
dc.date.issued2009en
dc.identifier.citationHosseini, S. M. E., Goh, W. L., & Chan, K. S. (2009). A general decoding framework for high-rate LDPC codes. In proceedings of the 12th International Symposium on Integrated Circuits: Singapore, (pp.695-698).en
dc.identifier.urihttps://hdl.handle.net/10356/99786-
dc.identifier.urihttp://hdl.handle.net/10220/6376en
dc.description.abstractThis paper presents a hardware solution to the design of general low-density parity-check (LDPC) decoders, which simplifies the delivery network required by the message passing algorithm. While many designs of LDPC decoders for specific classes of codes exist in the literature, the design of a general LDPC decoder capable of supporting random LDPC codes is still challenging. The method proposed in this paper tries to pack different check node (CN) and variable node (VN) messages in the Tanner graph representation of the LDPC code, and is therefore called message packing. This method takes advantage of the fact that for high-rate LDPC’s the CN’s degree is much larger than the VN’s, and two distinct methods for delivering the messages to the CNs and VNs are proposed. Using the proposed interconnection network (IN) results in lower complexity decoding of LDPC codes when compared to other designs.en
dc.format.extent4 p.en
dc.language.isoenen
dc.rights© 2009 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. http://www.ieee.org/portal/site This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.en
dc.subjectDRNTU::Engineering::Electrical and electronic engineering::Computer hardware, software and systemsen
dc.titleA general decoding framework for high-rate LDPC codesen
dc.typeConference Paperen
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen
dc.contributor.conferenceIEEE International Symposium on Integrated Circuits (12th : 2009 : Singapore)en
dc.contributor.organizationA*STAR Data Storage Instituteen
dc.identifier.openurlhttp://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=5403795en
dc.description.versionPublished versionen
item.grantfulltextopen-
item.fulltextWith Fulltext-
Appears in Collections:EEE Conference Papers
Files in This Item:
File Description SizeFormat 
A General Decoding Framework for High-rate LDPC Codes.pdf448.49 kBAdobe PDFThumbnail
View/Open

Google ScholarTM

Check

Items in DR-NTU are protected by copyright, with all rights reserved, unless otherwise indicated.