Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/99838
Title: A 5.61 pJ, 16 kb 9T SRAM with single-ended equalized bitlines and fast local write-back for cell stability improvement
Authors: Li, Qi
Wang, Bo
Kim, Tony Tae-Hyoung
Keywords: DRNTU::Engineering::Electrical and electronic engineering
Issue Date: 2012
Source: Li, Q., Wang, B., & Kim, T. T. (2012). A 5.61 pJ, 16 kb 9T SRAM with single-ended equalized bitlines and fast local write-back for cell stability improvement. ESSDERC 2012 - 42nd European Solid State Device Research Conference, pp.201-204.
Abstract: A 5.61 pJ, 16 kb 9T SRAM is implemented in 65nm CMOS technology. A single-ended equalized bitline scheme is proposed to improve both read bitline voltage swing and sensing timing window. A fast local write-back allows the half-select-free write operation without performance degradation. The test chip shows a minimum operating voltage of 0.24V and a minimum energy of 5.61pJ at 0.3V.
URI: https://hdl.handle.net/10356/99838
http://hdl.handle.net/10220/16227
DOI: 10.1109/ESSDERC.2012.6343368
Fulltext Permission: none
Fulltext Availability: No Fulltext
Appears in Collections:EEE Conference Papers

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