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Title: SRAM-based NATURE: A dynamically reconfigurable FPGA based on 10T low-power SRAMs
Authors: Jha, Niraj K.
Lin, Ting-Jung
Zhang, Wei
Keywords: DRNTU::Engineering::Computer science and engineering::Hardware::Logic design
Issue Date: 2012
Source: Lin, T. J., Zhang, W., & Jha, N. K. (2012). SRAM-based NATURE: A dynamically reconfigurable FPGA based on 10T low-power SRAMs. IEEE transactions on very large scale integration (VLSI) systems, 20(11), 2151-2156.
Series/Report no.: IEEE transactions on very large scale integration (VLSI) systems
Abstract: We presented a hybrid CMOS/nanotechnology reconfigurable architecture (NATURE), earlier. It was based on CMOS logic and nano RAMs. It used the concept of temporal logic folding and fine-grain (e.g., cycle-level) dynamic reconfiguration to increase logic density by an order of magnitude. This dynamic reconfiguration is done intra-circuit rather than inter-circuit. However, the previous design of NATURE required fine-grained distribution of nano RAMs throughout the field-programmable gate array (FPGA) architecture. Since the fabrication process of nano RAMs is not mature yet, this prevents immediate exploitation of NATURE. In this paper, we present a NATURE architecture that is based on CMOS logic and CMOS SRAMs that are used for on-chip dynamic reconfiguration. We use fast and low-power SRAM blocks that are based on 10T SRAM cells. We have also laid out the various FPGA components in a 65-nm technology to evaluate the FPGA performance. We hide the dynamic reconfiguration delay behind the computation delay through the use of shadow SRAM cells. Experimental results show more than an order of magnitude improvement in logic density and 3.48X improvement in the area-delay product relative to a traditional baseline FPGA architecture that does not use the concept of logic folding.
ISSN: 1063-8210
DOI: 10.1109/TVLSI.2011.2169996
Rights: © 2011 IEEE
Fulltext Permission: none
Fulltext Availability: No Fulltext
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