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Title: Modeling and layout optimization techniques for silicon-based symmetrical spiral inductors
Authors: Sia, Choon Beng
Lim, Wei Meng
Ong, Beng Hwee
Tong, Ah Fatt
Yeo, Kiat Seng
Keywords: DRNTU::Engineering::Electrical and electronic engineering
Issue Date: 2013
Source: Sia, C. B., Lim, W. M., Ong, B. H., Tong, A. F., & Yeo, K. S. (2013). Modeling and layout optimization techniques for silicon-based symmetrical spiral inductors. Progress in electromagnetics research, 143, 1-18.
Series/Report no.: Progress in electromagnetics research
Abstract: A scalable and highly accurate RF symmetrical inductor model (with model error of less than 5%) has been developed from more than 100 test structures, enabling device performance versus layout size trade-offs and optimization up to 10 GHz. Large conductor width designs are found to yield good performance for inductors with small inductance values. However, as inductance or frequency increases, interactions between metallization resistive and substrate losses render the use of large widths unfavorable as they consume silicon area and degrade device performance. These findings are particularly important when exploiting the cost-effective silicon-based RF technologies for applications with operating frequencies greater than 2.5 GHz.
ISSN: 1070-4698
Rights: © 2013 EMW Publishing. This paper was published in Progress In Electromagnetics Research and is made available as an electronic reprint (preprint) with permission of EMW Publishing. The paper can be found at the following official OpenURL: []. One print or electronic copy may be made for personal use only. Systematic or multiple reproduction, distribution to multiple locations via electronic or other means, duplication of any material in this paper for a fee or for commercial purposes, or modification of the content of the paper is prohibited and is subject to penalties under law.
Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:EEE Journal Articles

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