Now showing items 1-5 of 5
Design of a hybrid neural spike detection algorithm for implantable integrated brain circuits
Real time spike detection is the first critical step to develop spike-sorting for integrated brain circuits interface applications. Nonlinear Energy Operator (NEO) and absolute thresholding have been widely used as the ...
0.77 fJ/bit/search content addressable memory using small match line swing and automated background checking scheme for variation tolerance
This work reports a fully parallel match-line (ML) structure with an automated background checking (ABC) scheme. MLs are pre-charged to an intermediate level by a pulsed current source to minimize power. The proposed ABC ...
Sensing margin enhancement techniques for ultra-low-voltage SRAMs utilizing a bitline-boosting current and equalized bitline leakage
A small bitline sensing margin is one of the most challenging design obstacles for reliable ultra-low-voltage static random access memory (SRAM) implementation. This paper presents design techniques for bitline sensing ...
Retention time characterization and optimization of logic-compatible embedded DRAM cells
Logic-compatible 2T and 3T embedded DRAMs (eDRAM) have recently gained their popularity in embedded applications because of their high density and good voltage margin. The most important design requirements in eDRAM cells ...
Design of a power-efficient CAM using automated background checking scheme for small match line swing
This work reports a fully parallel match-line (ML) structure with an automated background checking (ABC) scheme. MLs are pre-charged by a pulsed current source to minimize power. The proposed ABC scheme monitors the ...