Now showing items 1-5 of 5
A temperature-dependent DC model for quarter-micron LDD pMOSFET’s operating in a Bi-MOS structure
A temperature-dependent analytical model for deep submicrometer LDD p-channel devices operating in a Bi-MOS structure is reported for the first time. This model is based on experimental data obtained from 0.25-µm process ...
A charge-trapping-based technique to design low-voltage BiCMOS logic circuits
New BiCMOS logic circuits employing a charge trapping technique are presented. The circuits include an XOR gate and an adder. Submicrometer technologies are used in the simulation and the circuits’ performances ...
A low-power 16×16-b parallel multiplier utilizing pass-transistor logic
This paper describes a low-power 16x16-b parallel very large scale integration multiplier, designed and fabricated using a 0.8- m double-metal double-poly BiCMOS process. In order to achieve low-power operation, the ...
Experimentally-based analytical model of deep-submicron LDD pMOSFET’s in a Bi-MOS hybrid-mode environment
The hybrid-mode operation of deep-submicron LDD pMOSFET’s has been investigated experimentally. Based on the experimental results, analytical models for the threshold voltage, the device currents, the transconductance, and ...
Comments on “Negative capacitance effect in semiconductor devices”
Capacitors play a very important role in the modeling of semiconductor devices. Without a good understanding and accurate model for the capacitance characteristics, one cannot model devices very well. The conventional ...