Now showing items 1-6 of 6
Design and analysis of ultra low power true single phase clock CMOS 2/3 prescaler
In this paper the power consumption and operating frequency of true single phase clock (TSPC) and extended true single phase clock (E-TSPC) frequency prescalers are investigated. Based on this study a ...
A fully-integrated low power PAM/PPM multi-channel UWB transmitter
A new transmitter for ultra-wideband (UWB) impulse radio is described in this paper. The proposed architecture features the simple design, low-power operation, and enables the ...
A subthreshold low-noise amplifier optimized for ultra-low-power applications in the ISM band
The IEEE 802.15.4 standard relaxes the requirements on the receiver front-end making subthreshold operation a viable solution. The specification is discussed and guidelines are presented for a small area ultra-low-power ...
A 3-8 GHz low-noise CMOS amplifier
A wideband CMOS low-noise amplifier (LNA) is ...
Parasitic-compensated quadrature LC oscillator
The paper presents a method for improving the phase noise performance of a CMOS quadrature LC oscillator through parasitic compensation. Owing to the parasitic resistance in the inductor, the LC oscillator suffers from a ...
Design of a hysteresis frequency lock detector for dual-loops clock and data recovery circuit
In dual-loops clock and data recovery (CDR) circuit design, lock detector is crucial in controlling the switching within CDR loop. The setting of the frequency accuracy of lock detector is a tough task as large ppm ...