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Scalable model of on-wafer interconnects for high-speed CMOS ICs
This paper describes the development of an equivalent circuit model of on-wafer interconnects for high-speed CMOS integrated circuits. By strategically cascading two- blocks together, the lumped model can characterize the ...
Sensitivity analysis of coupled interconnects for RFIC applications
This paper investigates the sensitivity of on-wafer coupled interconnects to the Si CMOS process parameters. Experiments are conducted to emulate state-of-the-art and future technologies. Some important parameters ...