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16.6- and 28-GHz fully integrated CMOS RF switches with improved body floating
(2008)
This paper presents two fully integrated CMOS
transmit/receive (T/R) switches with improved body-floating operations. The first design exploits an improved transistor layout with asymmetric drain–source region, which ...
A scalable RFCMOS noise model
(2009)
This paper presents the high-frequency (HF) noise
...
Sub-mW multi-GHz CMOS dual-modulus prescalers based on programmable injection-locked frequency dividers
(2008)
Dual-modulus prescalers based on
programmable Injection-Locked Frequency Dividers
(ILFDs) are ...
Design and analysis of ultra low power true single phase clock CMOS 2/3 prescaler
(2010)
In this paper the power consumption and operating
frequency of true single phase clock (TSPC) and extended true
single phase clock (E-TSPC) frequency prescalers are investigated.
Based on this study a ...
RFCMOS unit width optimization technique
(2007)
In this paper, we demonstrate a unit width (Wf) optimization technique based on their unity short-circuit current gain frequency (ft), unilateral power gain frequency (f MAX), and high-frequency (HF) noise for RFCMOS ...
Design and optimization of the extended true single-phase clock-based prescaler
(2006)
The power consumption and operating frequency of the extended true single-phase clock (E-TSPC)-based frequency divider is investigated. The short-circuit power and the switching power in the E-TSPC-based divider are ...
Sub-1 V low power wide range injection-locked frequency divider
(2007)
In this letter, the sub-1 V low power, wide range operation of an injection-locked frequency divider with a common-gate configuration is presented. The performances in terms of locking range and power consumption have been ...
A 1.8-V 2.4/5.15-GHz dual-band LC VCO in 0.18-μm CMOS technology
(2006)
A dual band, fully integrated, low phase-noise and low-power voltage-controlled oscillator (VCO) operating at the 2.4-GHz industrial scientific and medical band and 5.15-GHz unlicensed national information infrastructure ...
An 8-bit 200-MSample/s pipelined ADC with mixed-mode front-end S/H circuit
(2008)
This paper describes an 8-bit pipelined analog-to-digital converter (ADC) using a mixed-mode sample-and-hold (S/H)circuit at the front-end. The mixed-mode sampling technique reduces signal swings in pipelined ADCs while ...
Design of a CMOS broadband transimpedance amplifier with active feedback
(2010)
In this paper, a novel current-mode transimpedance amplifier (TIA) exploiting the common gate input stage with common source active feedback has been realized in CHRT 0.18 µm -1.8 V RFCMOS technology. The proposed active ...
