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      Ma, Jianguo (25)
      Yeo, Kiat Seng (25)
      Do, Manh Anh (24)Ma, Kaixue (5)Li, Erping (4)Lim, Wei Meng (4)Shi, Xiaomeng (4)Sia, Choon Beng (4)Yu, Xiao Peng (4)Boon, Chirn Chye (3)... View MoreDate2010 - 2012 (1)2000 - 2009 (23)1999 - 1999 (1)SubjectEngineering (23)... View More

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      A miniaturized silicon-based ground ring guarded patch resonator and filter 

      Ma, Kaixue; Ma, Jianguo; Sun, Jianbo; Miao, Jianmin; Do, Manh Anh; Yeo, Kiat Seng (2005)
      A new miniaturized ground ring guided microstrip patch filter developed on the silicon wafer using micromachined technology is reported. The ground shunt can be used to lower the operating frequency up to one-third as ...
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      A compact size coupling controllable filter with separate electric and magnetic coupling paths 

      Ma, Kaixue; Ma, Jianguo; Yeo, Kiat Seng; Do, Manh Anh (2006)
      This paper presents the characteristics of a miniaturized microstrip filter, which has two separate coupling paths: electric coupling path and magnetic coupling path between two resonators. Either magnetic coupling or ...
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      Scalable model of on-wafer interconnects for high-speed CMOS ICs 

      Shi, Xiaomeng; Yeo, Kiat Seng; Ma, Jianguo; Do, Manh Anh; Li, Erping (2006)
      This paper describes the development of an equivalent circuit model of on-wafer interconnects for high-speed CMOS integrated circuits. By strategically cascading two- blocks together, the lumped model can characterize the ...
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      Design and optimization of the extended true single-phase clock-based prescaler 

      Yu, Xiao Peng; Do, Manh Anh; Lim, Wei Meng; Yeo, Kiat Seng; Ma, Jianguo (2006)
      The power consumption and operating frequency of the extended true single-phase clock (E-TSPC)-based frequency divider is investigated. The short-circuit power and the switching power in the E-TSPC-based divider are ...
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      Sensitivity analysis of coupled interconnects for RFIC applications 

      Shi, Xiaomeng; Yeo, Kiat Seng; Ma, Jianguo; Do, Manh Anh; Li, Erping (2006)
      This paper investigates the sensitivity of on-wafer coupled interconnects to the Si CMOS process parameters. Experiments are conducted to emulate state-of-the-art and future technologies. Some important parameters ...
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      Sub-1 V low power wide range injection-locked frequency divider 

      Yu, Xiao Peng; Do, Manh Anh; Ma, Jianguo; Lim, Wei Meng; Yeo, Kiat Seng; Yan, Xiaolang (2007)
      In this letter, the sub-1 V low power, wide range operation of an injection-locked frequency divider with a common-gate configuration is presented. The performances in terms of locking range and power consumption have been ...
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      9.3–10.4-GHz-band cross-coupled complementary oscillator with low phase-noise performance 

      Lin, Jia; Ma, Jianguo; Yeo, Kiat Seng; Do, Manh Anh (2004)
      A fully integrated 10-GHz-band voltage-controlled oscillator (VCO) has been designed and fabricated using commercial 0.18- m CMOS technology. The complementary cross-coupled differential topology is adopted ...
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      Fully integrated CMOS fractional-N frequency divider for wide-band mobile applications with spurs reduction 

      Boon, Chirn Chye; Do, Manh Anh; Yeo, Kiat Seng; Ma, Jianguo (2005)
      A spurs reduction fractional-N frequency divider with a frequency range which is 3.5 times larger than that of a conventional fractional-N divider is presented in this paper. A 1.2-GHz quadrature voltage-controlled oscillator ...
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      A novel CMOS low-noise amplifier design for 3.1-to 10.6-GHz ultra-wide-band wireless receivers 

      Lu, Yang; Yeo, Kiat Seng; Cabuk, Alper; Ma, Jianguo; Do, Manh Anh; Lu, Zhenghao (2006)
      An ultra-wideband (UWB) 3.1- to 10.6-GHz low-noise amplifier (LNA) employing a common-gate stage for wideband input matching is presented in this paper. Designed in a commercial 0.18-um 1.8-V standard RFCMOS technology, ...
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      Physical layout design optimization of integrated spiral inductors for silicon-based RFIC applications 

      Sia, Choon Beng; Ong, Beng Hwee; Chan, Kwok Wai; Yeo, Kiat Seng; Ma, Jianguo; Do, Manh Anh (2005)
      A new test structure layout technique and design methodology are used to investigate quantitatively how geometrical layout parameters such as core diameter, conductor spacing, and width would affect the performance of ...
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