This paper describes the development of an equivalent circuit model of on-wafer interconnects for high-speed CMOS integrated circuits. By strategically cascading two- blocks together, the lumped model can characterize the ...

This paper investigates the sensitivity of on-wafer coupled interconnects to the Si CMOS process parameters. Experiments are conducted to emulate state-of-the-art and future technologies. Some important parameters ...

A model development methodology for complex shaped on-wafer interconnects is presented. The equivalent circuit of the entire interconnect is obtained by cascading ...

This paper investigates the properties of the on-wafer interconnects built in a 0.18-µm CMOStechnology for RF applications. A scalable equivalent circuit model is developed. The model parameters are extracted directly ...