Now showing items 1-4 of 4
A dual-loop clock and data recovery circuit with compact quarter-rate CMOS linear phase detector
This paper presents a 5-Gb/s dual-loop clock and data recovery (CDR) circuit with a compact quarter-rate linear phase detector (PD). The proposed PD not only reduces the complexity of the circuit structure but also employs ...
A new field dependent mobility model for high frequency channel thermal noise of deep submicron RFCMOS
In this paper, a new field dependent effective mobility model including the drain-induced vertical field effect (DIVF) is presented to calculate the channel thermal noise of short channel MOSFETs operating at high frequencies. ...
Design of a hysteresis frequency lock detector for dual-loops clock and data recovery circuit
In dual-loops clock and data recovery (CDR) circuit design, lock detector is crucial in controlling the switching within CDR loop. The setting of the frequency accuracy of lock detector is a tough task as large ppm ...
A 0.6-V high reverse-isolation through feedback self-cancellation for single-stage noncascode CMOS LNA
In many designs, a low supply voltage is selected for efficient use of power. However, this often leads to low reverse-isolation which is critical to the RF front–end circuits and particularly to the low-noise amplifier ...