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A dual-loop clock and data recovery circuit with compact quarter-rate CMOS linear phase detector
This paper presents a 5-Gb/s dual-loop clock and data recovery (CDR) circuit with a compact quarter-rate linear phase detector (PD). The proposed PD not only reduces the complexity of the circuit structure but also employs ...
Design of a hysteresis frequency lock detector for dual-loops clock and data recovery circuit
In dual-loops clock and data recovery (CDR) circuit design, lock detector is crucial in controlling the switching within CDR loop. The setting of the frequency accuracy of lock detector is a tough task as large ppm ...